Mentor Graphics Adds New Design Creation and Management Features for Complex FPGA Design in FPGA Advantage 5.3

WILSONVILLE, Ore.--(BUSINESS WIRE)--July 10, 2002--Mentor Graphics Corporation (Nasdaq: MENT - News) today introduced FPGA Advantage® 5.3, the latest version of its industry-leading HDL design flow for managing the creation, simulation and synthesis of field-programmable gate array (FPGA) devices.

FPGA Advantage 5.3 adds new design management features, including enhanced Interface-Based Design(TM) (IBD(TM)) support and advanced debugging features, which simplify and ease the design of multi-million gate FPGAs.

"Titan Aerospace Electronics is committed to developing next-generation FPGA designs that push current technological limits," said Robert Jacobson, principal engineer, Titan Aerospace Electronics. "Mentor's FPGA Advantage 5.3 tool allows design teams to design, manage, debug, simulate and synthesize our complex FPGA designs quickly and effectively. With this all-in-one tool, Mentor Graphics continues to raise the bar in developing state-of-the-art FPGA design solutions."

    Advances to FPGA Advantage 5.3 Include Enhanced Design Creation
    and Management Features

The FPGA Advantage 5.3 IBD editor solves problems design engineers have with complex interconnect creation. IBD allows complex interconnect structures to be viewed in a compact tabular format. Users can rapidly specify the signal connections and automatically generate the equivalent structural description in VHDL or Verilog. The IBD tabular format also enables design constraints and synthesis properties to be specified and then be propagated to the downstream phases of the design flow.

FPGA Advantage's debugging capabilities have been expanded with version 5.3 to include visualization of text files during interactive simulation debug. These graphical and tabular diagrams of HDL source code enhance HDL simulation and improve design verification productivity.

FPGA Advantage 5.3 provides additional enhancements for FPGA designers, including:

• Ability to add and remove hierarchy levels
• Frames for multiple instance instantiations
• Signal stubs for signal slicing
• Dataflow window X-tracing
• Support for Microsoft® Windows® XP

"Mentor Graphics continues to extend FPGA Advantage's capabilities to handle the latest device complexities from the FPGA market leaders," said Valerie Rachko, director of marketing, HDL design and FPGA solutions, Mentor Graphics. "Mentor is the only EDA tool vendor to offer an integrated FPGA design flow for design creation, debug, simulation and synthesis."

    Support for Altera's MegaWizard and LogicLock Programmable Logic
    Solutions

FPGA Advantage 5.3 adds Verilog support for Altera® Corporation's MegaWizard® Verilog plug-in manager and LogicLock(TM). The MegaWizard plug-in manager allows a designer to customize megafunctions in either VHDL or Verilog without changing the design's source code. LogicLock enables hierarchical and incremental design within the Altera Quartus® II design environment.

FPGA Advantage 5.3 continues to offer VHDL and Verilog support for Xilinx® CORE Generator(TM), allowing designers to incorporate large blocks of IP directly and seamlessly into the design flow for Xilinx devices.

Pricing and Availability

FPGA Advantage 5.3 is available immediately through the Mentor Graphics® unique multi-tiered distribution network. All versions of FPGA Advantage 5.3 support all major FPGA vendors. Customers have the ability to choose from an entry-level FPGA design flow solution designed for the single FPGA designer, starting at $12,000, to a complex FPGA design flow solution for workgroups starting at $45,000. Additional information on FPGA Advantage 5.3 can be found at www.fpga-advantage.com.

About Mentor Graphics Corporation

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.

Mentor Graphics and FPGA Advantage are registered trademarks of Mentor Graphics Corporation. Interfaced-Based Design and IBD are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

     Mentor Graphics
     Rebecca Granquist, 503/685-0702
     rebecca_granquist@mentor.com
     or
     Weber Shandwick
     Jason Khoury, 415/354-8391
     jkhoury@webershandwick.com